As the number of devices in a very large scale integrated (VLSI) circuit chip surpasses 10.sup.5, the individual transistor devices which form its component elementary logic circuits, occupy areas of the chip on the order of a few square microns. The quantity of charge which is transferred between field effect transistor devices of this size while carrying out normal switching operations, is on the order of 0.1 picoCoulombs (10.sup.-12 Coulombs), making them very susceptible to electrostatic perturbations.
One ubiquitous source of such perturbations is cosmic rays, a highly penetrating radiation apparently reaching the earth in all directions from outer space. The primary cosmic rays entering the earth's atmosphere are almost entirely composed of positively charged atomic nuclei which collide with air nuclei high in the atmosphere, forming showers of positively and negatively charged nuclear fragments called secondary cosmic rays. These secondary cosmic rays penetrate all matter at the earth's surface and as they pass through a material object, they undergo collisions with the electrons and nuclei of which the material is composed, leaving a track of electrostatic charge along the way. The linear charge density along such a track can be typically 0.1 picoCoulombs per micron, which is on the same scale as the quantity of charge involved in the switching operation of a single field effect transistor on a VLSI chip.
This becomes a significant problem in latch circuits composed of such devices, since a latch must sense and reliably store a binary bit of information for intervals measurable in millions of machine cycles. In order to better understand this problem, reference will be made to a typical integrated circuit field effect transistor latch and the mechanism of its response to an electrostatic perturbation such as cosmic ray, will be discussed.
To begin this description, several terms need to be defined and suitable abbreviations established. The N channel field effect transistor circuit technology will be the example used herein. The abbreviation NFET will be used herein to refer to an N channel field effect transistor device. Such devices are generally fabricated by forming an N-type conductivity source diffusion and N-type diffusion in the surface of a P-type conductivity silicon substrate. The channel region of the substrate separating the source and drain regions, is covered by a gate insulator layer and a gate electrode. An enhancement mode NFET is normally nonconducting between its source and drain and it can be switched into conduction by applying a positive potential to its gate electrode, with respect to the potential of its source. A depletion mode NFET is normally conducting between its source and drain and it can be switched into nonconduction by applying a negative potential to its gate electrode, with respect to the potential of its source.
A typical NFET integrated circuit latch 6 is shown in a portion of FIG. 1. The latch 6 is a level sensitive scan design (LSSD) latch which stores one binary bit of information, and can be used either to store a test bit during test operations or it can store a data bit during normal logic function operations. The latch 6 consists of a pair of cross-coupled inverters. The first inverter is composed of the NFET enhancement mode active device 50 and the NFET depletion mode load device 52 which are series-connected between the drain potential Vdd at 10 of approximately five volts and ground potential. The convention is adopted that the drain potential of Vdd represents a binary logic value of "1" and ground potential represents a binary logic value of "0."
In normal operation, when a binary "1" signal of Vdd potential is applied by the node 8 to the gate of device 50, the gate of device 50 is positively biased with respect to its source and therefore it conducts the current supplied by the load device 52, dropping the potential of the output node 8' of the inverter to the binary "0," ground potential. Alternately, when a binary "0" signal of ground potential is applied by the node 8 to the gate of device 50, the gate of device 50 is not positively biased with respect to its source and therefore it no longer conducts the current supplied by the load device 52. Thus, the load device 52 charges node 8' to a binary "1," at which time there is no longer a potential difference between its source and drain. That is, the binary "1" potential of Vdd exists at the output node 8' and the load device 52 is no longer conducting current. Since the gate electrode is connected to the source for the load device 52, it is never negatively biased with respect to the source and therefore the load device is always capable of supplying current to the node 8' whenever the potential of the node 8' is less than the drain potential Vdd.
As can be seen from FIG. 1, the latch 6 is made up of two inverters, the first inverter being devices 50 and 52 and the second inverter being devices 70 and 72. The second inverter is identical to the first inverter, devices 50 and 70 being both NFET enhancement mode devices and devices 52 and 72 being both NFET depletion mode devices. By cross-coupling the output node 8' of the first inverter to the gate of the active device 70 of the second inverter and cross-coupling the output node 8 of the second inverter to the gate of the active device 50 of the first inverter, positive feedback reinforcement of the present conduction state of each respective inverter is obtained. It is in this manner that a binary bit of information can be stored in the latch. By convention, when the first node 8' is at a higher potential than the second node 8, the latch 6 will be storing a binary "1" value and when the first node 8' is at a lower potential than the second node 8, the latch 6 will be storing a binary "0" value. The state of the binary bit stored in the latch 6 can be read by sensing the relative potential of the first node 8' with respect to the second node 8, or by sensing the individual nodes 8 or 8', exclusively.
In order to write a new data bit into the latch 6, a first data input circuit is connected to the first node 8' consisting of the series-connected NFET enhancement mode devices 12 and 16 and a second data input circuit is connected to the second node 8 consisting of the series-connected NFET enhancement mode devices 12' and 16'. The gates of devices 16 and 16' are connected to a write-enable (WE) input 14 which, when on, defines the write intervals when the state of the latch 6 can be changed. In LSSD terminology, the write-enable signal is also known as the "C-clock." If the DATA* input 15 to the gate of device 12 is on while the WE input 14 to the gate of device 16 is on, then the first node 8' is connected to ground potential and the latch 6 has its binary storage state changed to the "0" state. The use of the "*" notation herein following the expression for a binary logic variable, indicates the binary complement of that variable. Alternately, if the DATA input 15' to the gate of device 12' is on while the WE input 14 to the gate of device 16' is on, then the second node 8 is connected to ground potential and the latch 6 has its binary storage state changed to the "1" state.
If the latch 6 also has test inputs to accept LSSD scan string test bits then circuit testing is desired. In order to write a new scan bit into the latch 6, a first scan input circuit is connected to the first node 8' consisting of the series-connected NFET enhancement mode devices 76 and 74 and a second scan input circuit is connected to the second node 8 consisting of the series-connected NFET enhancement mode devices 76' and 74'. The gates of devices 74 and 74' are connected to the A-clock (A-CLK) input which, when on, defines the scan-write intervals when the state of the latch 6 can be changed. If the SCAN* input to the gate of device 76 is on while the A-CLK input to the gate of device 74 is on, then the first node 8' is connected to ground potential and the latch 6 has its binary storage state changed to the "0" state. Alternately, if the SCAN input to the gate of device 76' is on while the A-CLK input to the gate of device 74' is on, then the second node 8 is connected to ground potential and the latch 6 has its binary storage state changed to the "1" state.
The effect of an electrostatic perturbation, such as a cosmic ray, on the binary storage state of a latch can be better understood by examining the cross-sectional view of the structure of the first inverter in the latch 6, as is depicted in FIG. 2. The NFET enhancement mode active device 50 and the NFET depletion mode load device 52 are shown in FIG. 2 as being formed in the P-type silicon substrate 54. The load device 52 has its N-type drain 56 and its N-type source 58 formed in the P-type substrate 54, and the gate insulator and the gate electrode 60 formed over the channel region separating the source 58 and drain 56. The load device 52 is made a depletion mode by ion implanting an N-type dopant in the channel region thereof. The drain 56 is connected to the positive drain potential Vdd. The source 58 and the gate 60 are connected in common to the latch node 8'. The substrate 54 is connected to ground potential and therefore the source 58 and the drain 56, which are both N-type, form a reversed bias junction with the P-type substrate 54.
The active device 50 has its N-type drain 62 and its N-type source 64 formed in the P-type substrate 54, and the gate insulator and the gate electrode 66 formed over the channel region separating the source 64 and drain 62. The drain 62 is connected to the latch node 8' and the source 64 is connected to ground potential. When the latch 6 is in its binary "1" state, the first inverter has its output node 8' at the positive Vdd potential and the gate electrode 66 of the active device 50 is at ground potential, keeping the active device 50 nonconducting. The positive potential of the N-type drain diffusion 62 with respect to the ground potential of the substrate 54, creates a reversed bias PN junction 63 between the drain 62 and the substrate 54.
The reversed bias PN junction 63 forms a region which is depleted of charge carriers, bounded by a layer of electrons on the N-type side and by a layer of positive charges on the P-type side. This creates an electric field in the depleted region of junction 63 which will sweep out any free charges which may occur therein, causing a small current. If the electrostatically charged track of a cosmic ray 68 passes within the vicinity of the reversed bias PN junction 63, the charges liberated in the depletion region of the junction 63 are swept out, causing a current spike of up to 30 milliamperes for a duration of from 0.1 to 0.2 nanoseconds. The charges stored in the node 8' are conducted through the PN junction 63 to the substrate 54, thereby discharging the node 8', dropping its potential toward ground potential. If the electrostatic perturbation is sufficiently large, it will drop the potential of node 8' as low as one forward biased PN junction potential difference below the potential of substrate 54.
At this juncture, both the first node 8' and the second node 8 of the latch 6, are at approximately ground potential. Since both the depletion mode load 52 and the depletion mode load 72 are capable of supplying current to the nodes 8' and 8, respectively, whenever those nodes are at a lower potential than the drain potential Vdd, each load device 52 and 72 tries to drive its respective node 8' and 8 up in potential. Due to the random conditions of resistive and capacitive balance between the two nodes 8 and 8', the restored state of the latch 6 after the electrostatic perturbation is a random occurrence. If the restored state of the latch 6 is different from the original state prior to the perturbation, then a soft error has occurred.